1. Field of the Invention
The present invention relates to a method and apparatus for performing double buffering operations when an EISA bus master is accessing main memory on the memory bus. In particular, double buffers are provided which serve as posting buffers until a full line is obtained, thereby reducing host bus hold times.
2. Description of the Related Art
The personal computer industry is evolving quickly due to the increasing demand for faster, smaller and more power computers. The general structure of a personal computer system typically includes a microprocessor or host bus for interfacing one or more processors with main memory, an expansion bus such as the Extended Industry Standard Architecture (EISA) bus which is used to interface with one or more optional external plug-in logic circuit boards, and also an X bus for interfacing with a plurality of peripheral devices such as a keyboard and a floppy disk controller. In a multiprocessor system, the processors typically share the host bus to access the main memory.
The EISA bus specification was introduced several years ago and describes all of the parameters that must be followed for any device to interface with the EISA bus. For more details, please refer to U.S. Pat. No. 5,101,492, specifically Appendix A, which patent is hereby incorporated by reference. Thus, bus masters, DMA devices or any other devices designed to interface with the EISA bus must follow the EISA bus specifications. In particular, the EISA data bus is 32 bits wide and the EISA bus includes a clock signal which is typically approximately 8 MHz. Modern processors, such as the 80386 or i486 microprocessors by Intel, are designed to operate at significantly higher speeds then the EISA bus. Also, processors are incorporated into central processing units (CPUs) which may be designed to operate with larger and faster host buses. For example, host buses have been designed to operate at 25 megahertz (MHz) to over 33 MHz and may include up to 64 data bits or more.
Memory arrays are keeping pace with processor innovation. Dynamic Random Access Memories (DRAMs) typically used to implement main memory are slower than SRAMs but are typically interleaved to help keep pace with CPUs. EISA bus masters attached to the EISA bus require access to the main memory, typically through a bus controller interface attached between the host bus and the EISA bus. Access through the host bus may be necessary so that the CPUs can snoop the EISA addresses to perform cache write back or invalidation cycles if necessary. Due to the relatively slow clock speed and narrow data width defined for the EISA bus, it is undesirable for an EISA bus master requiring access to the main memory to tie up the host bus for its entire write or read cycle. This is especially true since the CPUs attached to the host bus must remain idle if they also require access to the main memory or the host bus.
It is desirable therefore to provide a buffering means to isolate the host bus and main memory from slower devices on the EISA bus such as EISA bus masters. Also, the devices accessing main memory should not detect any differences in access to the main memory.